Embodiments of the present invention relate to a communication interface between two devices. More specifically, the present invention pertains to a bi-directional serial interface which may interleave the data bits sent between a master device and a slave device.
Electronic devices may communicate using bus architectures. There are serial and parallel bus architectures. The I2C bus is one conventional communication bus for electronic devices. In this bus, there are two wires connecting a plurality of devices. One wire is the clock bus, the other is the data bus. The data is sent in eight-bit bytes across the data bus. While the I2C bus offers advantages over its predecessors in simplicity of design, reduced pin count, and low noise distortion, it is still not optimized for some forms of data transfer. By using eight-bit bytes, the flow of data is characterized by a series of starts and stops as the receiving circuitry clears the bytes of data. Importantly, data is sent serially in groups of bytes over the bus. In other words, while a byte is being transferred over a wire, no other transfer can take place until the byte transfer is complete.
Another conventional serial communication interface is the serial peripheral interface (SPI). The SPI has two data lines, one going out from the master into the slave, and one going out from the slave into the master, as well as a clock line and a chip select wire. This communication interface offers the advantage of enabling two-way communications. Its disadvantage is that the circuit is complicated by the greater number of wires needed.
It would be advantageous, then, to provide a system which combines the advantages of a simple architecture with the ability to conduct two-way simultaneous communications. The present invention provides a solution to meet the above needs.
Accordingly, the present invention allows for simultaneous bi-directional communication between two devices while providing a single data line interface architecture. By bit interleaving the data from the two devices over this single data line, data can be shifted into the registers while commands are being shifted out over a common data line. In situations where the commands to the slave are primarily read operations, there are far fewer starts and stops in the data flow. These and other objects and advantages of the present invention and others not specifically recited above will be described in more detail herein.
Embodiments of the invention are directed to a shared wire serial interface between two devices that share a system clock and a single bi-directional serial data line. The system clock drives both the system and the interface, and is provided over a single clock wire. One device operates as a master, the other as a slave. Since the master and slave share the same clock, clock drift will be zero. Although the start of a data transfer is asynchronous with regard to the system clock, the data transfer itself may be synchronous. In one embodiment, the bit transfer rate is a multiple of the system clock speed e.g., xe2x85x9th, and is generated by a state machine, however, any multiple may be used. The state machine also signals the output enablers which interleave the data bits on the serial data line. The flow of data on a single data line of the interface is bi-directional in that data from the master may be bit interleaved with data from the slave. Due to the bit interleaving of data between master and slave, the master can simultaneously shift a command out of its register while shifting in a reply from a previous command. A one bit tri-state period separates each data bit.
More specifically, the present invention provides a system for performing bit interleaved communication between two devices. The devices have an interface of a single bi-directional serial data line and a single system clock line Output enablers on both devices interleave the data bits in conjunction with a common system clock. A clock divider on each device regulates the transfer and reception of bit data between shift registers, which transfer data bytes to and from a memory area. In the present embodiment, the clock divider regulates this transfer at a multiple of the system clock frequency e.g., xe2x85x9th of the system clock. Each of the interleaved bits is followed by a tri-state period which is one bit time in duration.